Double Resistor Equipped Transistor RET Nexperia PIMC31 115 NPN PNP 50 Volt Surface Mount SOT457
Product Overview
The Nexperia PIMC31 is a 500 mA, 50 V NPN/PNP double Resistor-Equipped Transistor (RET) housed in a compact SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package. This component features built-in bias resistors, simplifying circuit design, reducing component count, and lowering pick-and-place costs. It is AEC-Q101 qualified, making it suitable for digital applications in automotive and industrial segments, particularly for switching loads.
Product Attributes
- Brand: Nexperia
- Package Type: SOT457 (SC-74)
- Technology: NPN/PNP double Resistor-Equipped Transistor (RET)
- Qualification: AEC-Q101
Technical Specifications
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| General | ||||||
| VCEO | Collector-emitter voltage (per transistor) | Open base; for the PNP transistor with negative polarity | - | - | 50 | V |
| IO | Output current (per transistor) | - | - | - | 500 | mA |
| R1 | Bias resistor 1 (input) | - | 0.7 | 1 | 1.3 | k |
| R2/R1 | Bias resistor ratio | - | 9 | 10 | 11 | - |
| Limiting Values | ||||||
| VCBO | Collector-base voltage (per transistor) | Open emitter; for the PNP transistor with negative polarity | - | - | 50 | V |
| VEBO | Emitter-base voltage (per transistor) | Open collector | - | - | 5 | V |
| VI (TR1) | Input voltage (TR1) | Positive | - | - | 10 | V |
| VI (TR1) | Input voltage (TR1) | Negative | -5 | - | - | V |
| VI (TR2) | Input voltage (TR2) | Positive | - | - | 5 | V |
| VI (TR2) | Input voltage (TR2) | Negative | -10 | - | - | V |
| Thermal Characteristics | ||||||
| Ptot | Total power dissipation (per device) | Tamb 25 C [1] | - | - | 420 | mW |
| Tj | Junction temperature | - | - | - | 150 | C |
| Tamb | Ambient temperature | - | -55 | - | 150 | C |
| Tstg | Storage temperature | - | -65 | - | 150 | C |
| Characteristics (Tamb = 25 C unless otherwise specified) | ||||||
| ICBO | Collector-base cut-off current (per transistor) | VCB = 50 V; IE = 0 A | - | - | 100 | nA |
| ICEO | Collector-emitter cut-off current (per transistor) | VCE = 50 V; IB = 0 A | - | - | 0.5 | A |
| IEBO | Emitter-base cut-off current (per transistor) | VEB = 5 V; IC = 0 A | - | - | 0.72 | mA |
| hFE | DC current gain (per transistor) | VCE = 5 V; IC = 50 mA | 70 | - | - | - |
| VCEsat | Collector-emitter saturation voltage (per transistor) | IC = 50 mA; IB = 2.5 mA | - | - | 0.3 | V |
| VI(off) | Off-state input voltage (per transistor) | VCE = 5 V; IC = 100 A | 0.3 | 0.6 | 1 | V |
| VI(on) | On-state input voltage (per transistor) | VCE = 0.3 V; IC = 20 mA | 0.4 | 0.8 | 1.4 | V |
| Cc | Collector capacitance (per transistor) | VCB = 10 V; IE = ie = 0 A; f = 1 MHz | - | 7 (TR1) / 11 (TR2) | - | pF |
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
2410121933_Nexperia-PIMC31-115_C426860.pdf
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