SOT363 Package Nexperia PUMD10 125 NPN PNP Resistor Equipped Double Transistor for Controlling IC Inputs
PUMD10: NPN/PNP Resistor-Equipped Double Transistor
Product Overview
The PUMD10 is a highly integrated NPN/PNP double Resistor-Equipped Transistor (RET) designed for efficient circuit simplification and component count reduction. Housed in a compact SOT363 (SC-88) SMD plastic package, this device features built-in bias resistors, enabling straightforward circuit design and reduced manufacturing costs. It is ideal for low current peripheral driving, controlling IC inputs, and as a replacement for general-purpose transistors in digital applications.
Product Attributes
- Brand: Nexperia
- Package Type: SOT363 (SC-88)
- Technology: NPN/PNP Double Transistor with integrated resistors
Technical Specifications
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| General & Per Transistor | ||||||
| VCEO | Collector-emitter voltage | Open base (for PNP transistor TR2 with negative polarity) | - | - | 50 | V |
| IO | Output current | - | - | - | 100 | mA |
| R1 | Bias resistor 1 (input) | [1] | 1.54 | 2.2 | 2.86 | k |
| R2/R1 | Bias resistor ratio | [1] | 17 | 21 | 26 | - |
| VCBO | Collector-base voltage | Open emitter | - | - | 50 | V |
| VCEO | Collector-emitter voltage | Open base | - | - | 50 | V |
| VEBO | Emitter-base voltage | Open collector | - | - | 5 | V |
| VI | Input voltage | Positive (input voltage TR1) | - | - | 12 | V |
| VI | Input voltage | Negative (input voltage TR1) | - | -5 | - | V |
| VI | Input voltage | Positive (input voltage TR2) | - | - | 5 | V |
| VI | Input voltage | Negative (input voltage TR2) | - | -12 | - | V |
| Ptot | Total power dissipation | Tamb 25 C [1] (Per device) | - | - | 300 | mW |
| Tj | Junction temperature | - | - | - | 150 | C |
| Tamb | Ambient temperature | - | -65 | - | 150 | C |
| Tstg | Storage temperature | - | -65 | - | 150 | C |
| Thermal Characteristics | ||||||
| Rth(j-a) | Thermal resistance junction to ambient | In free air [1] (Per transistor) | - | - | 625 | K/W |
| Rth(j-a) | Thermal resistance junction to ambient | In free air [1] (Per device) | - | - | 417 | K/W |
| Characteristics (Tamb = 25 C unless otherwise specified) | ||||||
| V(BR)CBO | Collector-base breakdown voltage | IC = 100 A; IE = 0 A | 50 | - | - | V |
| V(BR)CEO | Collector-emitter breakdown voltage | IC = 2 mA; IB = 0 A | 50 | - | - | V |
| ICBO | Collector-base cut-off current | VCB = 50 V; IE = 0 A | - | - | 100 | nA |
| ICEO | Collector-emitter cut-off current | VCE = 30 V; IB = 0 A | - | - | 100 | nA |
| ICEO | Collector-emitter cut-off current | VCE = 30 V; IB = 0 A; Tj = 150 C | - | - | 5 | A |
| IEBO | Emitter-base cut-off current | VEB = 5 V; IC = 0 A | - | - | 180 | A |
| hFE | DC current gain | VCE = 5 V; IC = 10 mA | 100 | - | - | - |
| VCEsat | Collector-emitter saturation voltage | IC = 5 mA; IB = 0.25 mA | - | - | 100 | mV |
| VI(off) | Off-state input voltage | VCE = 5 V; IC = 100 A | - | 0.6 | 0.5 | V |
| VI(on) | On-state input voltage | VCE = 0.3 V; IC = 5 mA | 1.1 | 0.75 | - | V |
| R1 | Bias resistor 1 (input) | [1] | 1.54 | 2.2 | 2.86 | k |
| R2/R1 | Bias resistor ratio | [1] | 17 | 21 | 26 | - |
| Cc | Collector capacitance | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz (TR1 NPN) | - | - | 2.5 | pF |
| fT | Transition frequency | VCE = 5 V; IC = 10 mA; f = 100 MHz [2] (TR1 NPN) | - | 230 | - | MHz |
| Cc | Collector capacitance | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz (TR2 PNP) | - | - | 3 | pF |
| fT | Transition frequency | VCE = 5 V; IC = 10 mA; f = 100 MHz [2] (TR2 PNP) | - | 180 | - | MHz |
[1] See section "Test information" for resistor calculation and test conditions.
[2] Characteristics of built-in transistor
Package Information
Package: TSSOP6 (SOT363)
Body Dimensions: 2.1 mm x 1.25 mm x 0.95 mm
Pitch: 0.65 mm
Ordering Information
Type Number: PUMD10
Marking
Marking Code: D%0 (where % is a placeholder for manufacturing site code)
Complementary Products
- PNP/PNP complement: PUMB10
- NPN/NPN complement: PUMH10
2410121943_Nexperia-PUMD10-125_C553504.pdf
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